According to provided details, companies have applied advanced scaling and wafer bonding technologies in order to achieve higher capacity, performance, and reliability, all while keeping the cost down, making it "ideal for meeting the needs of exponential growth across a broad range of market segments."

Companies are using a balance between vertical and lateral scaling in order to come up with greater capacity in a smaller die with fewer layers, at an optimized cost. They use the CBA (CMOS directly Bonded to Array) technology, which means that each CMOS wafer and cell array wafer is manufactured separately, and then bonded together.

The new 218-layer 3D flash uses 1Tb triple-level-cell (TLC) and quad-level-cell (QLC) with four planes with innovative lateral shrink technology which increased bit density by 50 percent. With high-speed NAND I/O reaching 3.2Gb/s, which in a 60 percent improvement over the previous generation, combined with a 20 percent write performance and read latency improvement, lead to higher overall performance and usability for users, according to statements.

"Through our unique engineering partnership, we have successfully launched the eighth-generation BiCS FLASH with the industry's highest bit density," said Masaki Momodomi, Chief Technology Officer at Kioxia Corporation. "I am pleased that Kioxia's sample shipments for limited customers have started. By applying CBA technology and scaling innovations, we've advanced our portfolio of 3D flash memory technologies for use in a range of data-centric applications including smartphones, IoT devices and data centers."

"The new 3D flash memory demonstrates the benefits of our strong partnership with Kioxia and our combined innovation leadership," said Alper Ilkbahar, Senior Vice President of Technology & Strategy at Western Digital. "By working with one common R&D roadmap and continued investment in R&D, we have been able to productize this fundamental technology ahead of schedule and deliver high-performance, capital-efficient solutions."