Codenamed Seattle, the chip will use ARM’s 64-bit ARMv8 architecture. With Seattle, AMD hopes to repeat the success of its first 64-bit x86 Opteron parts from a decade ago. The focus is on dense server space and power efficiency. The ARMv8 architecture more than doubles the word-length compared to the previous ARMv7 instruction set. Seattle parts will feature four to eight cores, with support for up to 128GB of ECC memory, Integrated 10Gb/sec Ethernet connectivity.
Seattle is for clearly for networks, but AMD points out that it is in a unique position to ship mixed racks with 64-bit ARM chips and traditional 64-bit x86 parts. This should allow the company to leverage the power efficiency and networking prowess of Seattle with upcoming x86 Opterons that will do most of the heavy lifting.
You can check out the details on AMD’s blog.
